Videos find
Whiteboard Wednesdays - Low Power SoC Design with High-Level Synthesis
3:38
Whiteboard Wednesdays - Low Power SoC Design with High-Level Synthesis
by Cadence Design Systems
Arteris IP: Implementing Low-Power AI SoCs Using NoC Interconnect Technology
27:52
Arteris IP: Implementing Low-Power AI SoCs Using NoC Interconnect Technology
by The Linley Group
FPGA Vision - Low-Power Design
15:49
FPGA Vision - Low-Power Design
by Marco Winzker (Professor)
NOC IP- Transforming Chip Communication​​​​​​​
24:15
NOC IP- Transforming Chip Communication​​​​​​​
by Truechip
Designing System-on-chip with NoC (Network-on-Chip), HBM2.0 (High Bandwidth Memory), DDR5, ARM Z1
59:54
Designing System-on-chip with NoC (Network-on-Chip), HBM2.0 (High Bandwidth Memory), DDR5, ARM Z1
by VisualSimSolutions
Power Optimization Techniques for NOC
10:44
Power Optimization Techniques for NOC
by IJERT
NoC Power-Management Advantages
32:34
NoC Power-Management Advantages
by designreuse
Introduction to PSoC® 4 BLE (Programmable System-on-chip with Bluetooth® Low Energy)
2:45
Introduction to PSoC® 4 BLE (Programmable System-on-chip with Bluetooth® Low Energy)
by Cypress Semiconductor
Veltech University_DESIGN OF 3D NoC ROUTER ARCHITECTURE FOR MULTICORE SoC
10:10
Veltech University_DESIGN OF 3D NoC ROUTER ARCHITECTURE FOR MULTICORE SoC
by Waikhom Reshmi
Network on Chip (NoC) with FPGAs|Part 1|Introduction
14:31
Network on Chip (NoC) with FPGAs|Part 1|Introduction
by Vipin Kizheppatt
Exploring the Power and Performance of Network on Chip Architecture for System-on-Chip
42:01
Exploring the Power and Performance of Network on Chip Architecture for System-on-Chip
by VisualSimSolutions
Synopsys End-to-End Solution for Energy-Efficient SoCs
2:35
Synopsys End-to-End Solution for Energy-Efficient SoCs
by EE Journal
How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster
17:33
How Arteris Enabling SoC Developers to Create Physically Valid NoCs Faster
by EE Journal
System on Chip (SoC) Power Tree: How to Design a Bus Regulator
44:34
System on Chip (SoC) Power Tree: How to Design a Bus Regulator
by Monolithic Power Systems | MPS
Addressing the #1 SoC development challenge with network on chip interconnect technology
19:25
Addressing the #1 SoC development challenge with network on chip interconnect technology
by designreuse
Arteris IP: A Flexible Multiprotocol Cache Coherent Network-on-Chip (NoC) for Heterogeneous SoCs
25:29
Arteris IP: A Flexible Multiprotocol Cache Coherent Network-on-Chip (NoC) for Heterogeneous SoCs
by The Linley Group
Low Power Design and Verification
15:53
Low Power Design and Verification
by Semiconductor Engineering
HC28-S3: Energy-Efficient Computing—Low-Power SoCs
59:16
HC28-S3: Energy-Efficient Computing—Low-Power SoCs
by hotchipsvideos
Implementing a Comprehensive Networks-on-Chip Generator with Optimal Configurations
1:25
Implementing a Comprehensive Networks-on-Chip Generator with Optimal Configurations
by IEEEComputerSociety
Wireless NoC for VFI Enabled Multicore Chip Design Performance Evaluation and Design Trade offs
3:30
Wireless NoC for VFI Enabled Multicore Chip Design Performance Evaluation and Design Trade offs
by IEEEComputerSociety